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  1. #1
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    CPU, DRAM, VNAND - why can't they be integrated together on a single SoC?

    Could someone please take a moment to explain what the technical blocker are, that currently prevent CPU's, DRAM, VNAND and all the appropriate controllers all being integrated together on a single SoC die?

    I understand that economically it may not be an optimal solution. But cost-no-object, and assuming all the appropriate licenses are obtained, I would really like to put a block of DRAM on the same die as a small ARM CPU core, together with some VNAND storage on there too - and for this project I do not care about yield figures. Two different foundries have told me it can't be done on the same process. As a non-expert, I'm just trying to understand why not?

    Thanks in advance, for any and all insights.

    Ross.

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  2. #2
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    Re: CPU, DRAM, VNAND - why can't they be integrated together on a single SoC?

    Aside from the CPU, the memories want different things.
    DRAM (optimized for cost) wants trench capacitors or at
    least capacitors optimized for areal density. Meanwhile
    "VNAND" (or any EE memory) wants an oxide / dielectric
    that well tolerates repeated current stress (which normal
    reliable FETs would prohibit) and high voltage programming
    features, which DRAM and CPU don't need.

    You can find technologies with EE features. These could
    be used for CPU ("it's just gates") and DRAM (if you can
    tolerate the inferior density - SRAM might fit tighter if you
    have XXnm FETs, and is likely already supported in flash
    memory technologies).

    It's not a matter of "can't", it's a matter of competitiveness
    (commercial mass market) or customers (heavy freight to
    pay, all that up front NRE against a probably limited lifetime
    quantity).

    Of all the problem s I'd call EE reliability the biggest / most
    technology-application-limiting. If you can get access to a
    flow that satisfies the nonvolatile retention / wearout issues,
    most other "stuff" could be made (perhaps at way inferior
    density).

    DRAM is so dirt cheap, you'd be mis-spending money to
    integrate that on a non-optimized flow, is my opinion. But
    lots of people seem to think that "system on a chip" means
    "entire system on a chip" and you'll be set. Neglecting such
    minor details as multi-rail and dead quiet power supplies,
    and how a bazillion transistors talk usefully to the outside
    world with no added help.

    Given that it doesn't, really, I see little glory in pulling DRAM
    onto the die (where you will pay for all the umpteen levels
    of fine pitch interconnect it doesn't need or want, and all
    the multiple FET species likewise, attending a modern SoC
    flow, yet never get the special capacitor you need for
    density).

    But "by any means necessary", yes you could. Not at the
    foundries you've contacted, with the relationship you've
    got, I guess.


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  3. #3
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    Re: CPU, DRAM, VNAND - why can't they be integrated together on a single SoC?

    dick's answer is really thorough. it's all about the trade-off of market needs vs cost. we are not in a situation where most customers would benefit from embedded DRAM or NVM, so you got to pay a lot of extra money to get those features from the foundry.
    Really, I am not Sam.



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  4. #4
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    Re: CPU, DRAM, VNAND - why can't they be integrated together on a single SoC?

    Agreed, DF definitely answered my original question, that's its more an economic limitation than a technical one. If the application required it, and your budget could stretch high enough, it could be done.

    The technical bottleneck appears to be that you'd need to build everything on your DRAM process, and then have to just swallow the high costs for the other components being made on that same process, and you just have to accept that small volume custom DRAM runs would be heinously expensive.

    Another takeaway from DF's points is that, depending on your specific requirements, it might be worth considering other types of memory and storage. It might be feasible (economical) to use alternative approaches, such as using SRAM instead of DRAM, to accomplish the same task.

    And his point about the relationship with the foundry is a subtle, but important factor too.

    Some great insights, and exactly what I was looking for.

    Ross.



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