Is anyone aware of a complete detailed description of the older commercial CMOS manufacturing processes, something between 1um to 2um node?
There a lot of simplified process flows out there, and each of them appears to skip different steps. So I could not find an exact answer on some of the question, e.g. at what point they started adding LDD, channel stop implants, silicide, planarization, etc. What are the must have features to make a reliable CMOS ASIC with 1um and 2um gate lengths?
Thanks a lot in advance!