Junus2012
Advanced Member level 5
Dear friends,
I am trying to design a floded cascode OTA for the sample and hold circuit that should work with sampling frequency of 5 MHz, this requires me to have an OTA with a typical GBW of 100 MHz. I am using 0.35 um CMOS technology with channel length I st for all the transistors to 1 um.
The problem I am finding it very difficuilt to achieve this GBW, I am using 120 uA for biasing my differential pairs with W/L = 60 (PMOS type )
I am thinking if I reduce the channel length I should expect a wider GBW, is it could method ? what is the typical minimum length I should use in my technology to keep other OTA properties as well ?
Thanks
I am trying to design a floded cascode OTA for the sample and hold circuit that should work with sampling frequency of 5 MHz, this requires me to have an OTA with a typical GBW of 100 MHz. I am using 0.35 um CMOS technology with channel length I st for all the transistors to 1 um.
The problem I am finding it very difficuilt to achieve this GBW, I am using 120 uA for biasing my differential pairs with W/L = 60 (PMOS type )
I am thinking if I reduce the channel length I should expect a wider GBW, is it could method ? what is the typical minimum length I should use in my technology to keep other OTA properties as well ?
Thanks