Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] if else statement inside an always block

Status
Not open for further replies.

rogger201

Newbie level 6
Joined
Sep 23, 2019
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
109
Hello,

I am using an if else block inside an always @(clock) block. My question is, the if statement is governed by a select and my sensitivity list does not contain this signal as its driven by clock and reset.
Is this a correct representation of the code:

Code:
always @(posedge CLK or negedge RST) begin 
if (!RST) shift_reg <= input_data;
else 
begin
   if (data_sel == 2'b11)
      begin 
      if (flag) shift_reg <= shift_reg;
      else shift_reg <= "do something else (some logic)";
      end 
   else shift_reg <= shift_reg;
end

The inside if statement is governed by data_sel which is not in the sensitivity list. Is this wrong or is there some other way to implement this logic?
 

Sensitivity list entries are neither required nor allowed for the synchronous (CLK edge sensitive) part of the always statement.

The "shift_reg <= shift_reg" statements are however useless and can be omitted. All registers are keeping there previous value unless assigned a new one.
 

Sensitivity list entries are neither required nor allowed for the synchronous (CLK edge sensitive) part of the always statement.

The "shift_reg <= shift_reg" statements are however useless and can be omitted. All registers are keeping there previous value unless assigned a new one.

I understand. This works as there are only 2 cases. But if i have more than two cases, I will have to use "CASE" which requires its own always block like
Code:
 always @(data_sel) 
case (data_sel)
...
How can I synchronize this with the clock?
 

But if i have more than two cases, I will have to use "CASE" which requires its own always block
No. You can use a case statement or any other sequential statement inside the clock edge controlled part of the always block.

Sensitivity list entries are required for combinational input signals and the clock.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top