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  1. #1
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    What is the difference between LVS and ERC ?

    What is the difference between LVS and ERC?
    is ERC is part of LVS or it is a separate check?
    in Assura, I can see two-run options (Run LVS & Run ERC).
    with the help of switch option, I can check antenna error while (I'm assuming it is ERC) running DRC.

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  2. #2
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    Re: What is the difference between LVS and ERC ?

    - LVS means Layout versus Schematic comparison
    - ERC means Electrical Rules' Check
    - DRC means layout Design Rules' Check

    These all are necessary checks with their own rules' sets. Depending on the PDK set-up, they can be called as separate checks, or all together (in series).

    - ARC, the Antenna Rules' Check actually is an electrical safety check (for safe silicon production), but uses layout design rules.


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    Re: What is the difference between LVS and ERC ?

    To extend a little bit (or to give examples of checks) on what erikl already explained:

    * LVS (Layout Versus Schematic comparison) - does the following things:

    - net connectivity extraction (determines the connectivity between the polygons)
    - device recognition (identifies the devices - like MOSFET, design resistors, design capacitor, diodes, etc.)
    - layer derivation (for example, calculates gate poly and field poly layers from poly and active layers)
    - cross-referencing between schematic and layout
    - calculates layout-dependent instance parameters for device instances (such as gate width and length, area/perimeter for source/drain, well proximity effect, LOD effect, etc.)
    - etc.

    * DRC (Design Rule Checking) - checks various rules, such as:

    - metal line widths
    - spacings between different layers
    - metal density
    - etc.

    (in modern technologies there thousands or tens of thousands of such rules)


    * ERC (Electrical Rule Checks) - verifies various things related to electrical behavior:

    - resistance rules (e.g. resistance from a pad to ESD diodes, from ESD diodes to power clamps, resistance to guard rings, etc.)
    - current density rules (ESD current densities, etc.)
    - voltage polarity checks (for example - checks that one of the parasitic diodes are forward biased)
    - voltage domains checks
    - latchup checks
    - etc.

    Max


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