bravo1234
Newbie level 5
Please find the attached simulation and required verilog files (notepad).
If you see the simulation ,you would notice 00x values as output and it is in red. It is expected that the output is 3 bit number instead of 00x. I am unable to rectify the problem. (Modelsim starter edition)
I have tried to make sure
1. The port connections between modules is right.
2. wire declarations
3.Checked the output of individual modules its perfect.
Please help.
View attachment Pulse_detector.txtView attachment Axel_final_count.txtView attachment Uni_D.txt
If you see the simulation ,you would notice 00x values as output and it is in red. It is expected that the output is 3 bit number instead of 00x. I am unable to rectify the problem. (Modelsim starter edition)
I have tried to make sure
1. The port connections between modules is right.
2. wire declarations
3.Checked the output of individual modules its perfect.
Please help.
View attachment Pulse_detector.txtView attachment Axel_final_count.txtView attachment Uni_D.txt