mvj
Advanced Member level 4
Hi,
The circuit in the picture is a complementary (NMOS & PMOS) Negative resistance core of an LC VCO. L, C and varactor are OFF-CHIP components connected across pins (IP,IP1B) and (IP1,IPB). The supply is a regulator output VREG and current in the oscillator is determined by resistors connected at top and bottom of the Negative resistance core. There is a capacitor (circled) connected across the common source point of PMOS and NMOS devices. This is what I am not sure of. I notice a significant improvement in phase noise for certain range of cap values. Below and above this range the phase noise degrades. My understanding is that this is some sort of a noise trap at twice the VCO oscialltion freq. Usually such a capacitor is accompanied by an inductor and the both resonate at twice the VCO freq and I don’t see any inductor here. May I know how this cap is helping improve phase noise and how to determine its value.
Thank you,
mvj
The circuit in the picture is a complementary (NMOS & PMOS) Negative resistance core of an LC VCO. L, C and varactor are OFF-CHIP components connected across pins (IP,IP1B) and (IP1,IPB). The supply is a regulator output VREG and current in the oscillator is determined by resistors connected at top and bottom of the Negative resistance core. There is a capacitor (circled) connected across the common source point of PMOS and NMOS devices. This is what I am not sure of. I notice a significant improvement in phase noise for certain range of cap values. Below and above this range the phase noise degrades. My understanding is that this is some sort of a noise trap at twice the VCO oscialltion freq. Usually such a capacitor is accompanied by an inductor and the both resonate at twice the VCO freq and I don’t see any inductor here. May I know how this cap is helping improve phase noise and how to determine its value.
Thank you,
mvj