MSAKARIM
Full Member level 3
I'm working on VHDL coding of a system has two inputs (say input A has 128 bit and input B has 256 bit) i'm using Virtex5. After synthesis Xillinix ISE gives me error that IOB not enough. how can i avoid this problem?
this is my entity
this is my entity
Code:
ENTITY ro IS
PORT(RST,CLK:IN STD_LOGIC;
A : IN std_logic_vector(127 downto 0);
B : IN std_logic_vector(255 downto 0);
C : OUT std_logic_vector(127 downto 0));
END ro;