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Not enough IOB of a certain FPGA

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MSAKARIM

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I'm working on VHDL coding of a system has two inputs (say input A has 128 bit and input B has 256 bit) i'm using Virtex5. After synthesis Xillinix ISE gives me error that IOB not enough. how can i avoid this problem?

this is my entity
Code:
ENTITY ro IS
PORT(RST,CLK:IN STD_LOGIC;
    A      :	IN  std_logic_vector(127 downto 0);
    B	        :	IN  std_logic_vector(255 downto 0);
    C    :	OUT std_logic_vector(127 downto 0));
END ro;
 

wwfeldman

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I'm working on VHDL coding of a system has two inputs (say input A has 128 bit and input B has 256 bit) i'm using Virtex5. After synthesis Xillinix ISE gives me error that IOB not enough. how can i avoid this problem?
where are you getting 128 bit parallel input, and 256 bit parallel input?
it takes a lot of PWB space, but 16 74299 type 8 bit universal shift registers would do it
and you would need to reconvert it to parallel inside the FPGA

and you would need 32 for the 256 bit datum

and you would need some circuits to load the data into the shift registers and then shift the data out

if one is clever, the 32 shift registers can also cover the 16. you would need to add
multiplexors or tri-state latches to do this

barry's suggestion of an FPGA with more I/O looks a lot easier
 

KlausST

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Hi,

Are you sure you need
* 256 input lines and
* another 128 input lines
....and where is the output?

Klaus
 

FvM

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I fear you are reading too much into the problem. Too me it looks like a trivial FPGA exercise, unfortunately compiled with a too small device, e.g. using automatic device selection in ISE. As long as you are not designing real hardware, where costs and board space matters, just select a device with sufficient number of IOB, Virtex 5 series surely has.
 

KlausST

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Hi,

The text clearly talks just about inputs "a system has two inputs (say input A has 128 bit and input B has 256 bit) "
A see that the code uses outputs...

Klaus
 

dpaul

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Hello OP,

Are you sure you need
* 256 input lines and
* another 128 input lines
....and where is the output?
This looks like an internal module design to me. At the peripheral you don't have these many signals.
If you provide us the project details then perhaps there can be more help.

btw - you run a simulation using a testbench for such a model, but for FPGA implementation you have to be realistic with the IO pin count.
 

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