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Can a gated input clock be a problem for a design?

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player80

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I'm trying to implement an SPI slave and I'm experiencing some issues with the ICE40up that the whole design seems to be stuck if I stop sending data from the SPI master.
I do not see any issues in the simulation.

The SPI clock is more or less a gated clock from the master (asic), and enters a gbuf input could that be a problem?
 

Hi,

confusing description.

Is this true:

ASIC as SPI master --> [SPI] --> ICE40UP as SPI slave

How do you detect the "stuck"?

In my eyes on an SPI system only the master can "be stuck".

***
If the master stops sending data --> it is quite usual that all SPI lines don´t change state.

****
Show your circuit / wiring.
Did you write the code for the ASIC? --> show us the code
Did you write the code for the ICE40UP? --> show us the code
Show the simulation results.
Show the real circuit behaviour (scope picture, logic analyzer)
Tell us what you expect ... and what is not like expected.

Klaus

added:
Please verify @ ASIC:
* V_IL
* V_IH
* V_OL
* V_OH
* operational input voltage range

And the same at the ICE40UP
 

Hi,

thank you for your reply.
I guess I was a bit too fast.

My SPI implementation itself seems to be fine, however I am messing up the timing it seems, and I'm able to break it at very simple conditions it seems.
Seems like I hit a perfect example how to do something wrong for learning... I'll post an update as soon as I figure out what's wrong.

seems like the gated input clock (SPI clock) from the master is not the issue and that's just what I wanted to be sure about.
 

Hi,

I wonder... what's the problem with SPI timing?

SPI is just a synchronous serial interface. Basically you just need parallel--serial shift registers and serial--parallel shift registers.

There should be plenty of HDL codes available in the internet.
Thus I recommend to look for one of those with good, detailed description.
I assume there are even video tutorials.
No need to reinvent the wheel.

Klaus
 

Hi,

the problem was the SPI Master the raspberry pi corrupts the spi stream once it exceeds 31.25 mhz.
I was looking at the wrong side not the FPGA was the problem. SPI is pretty easy to describe with VHDL.
 

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