+ Post New Thread
Results 1 to 5 of 5
  1. #1
    Newbie level 2
    Points: 26, Level: 1

    Join Date
    Feb 2019
    Posts
    2
    Helped
    0 / 0
    Points
    26
    Level
    1

    Help to synthesize floating point MAC in Design Compiler using DesignWare library.

    Hi,
    I'm new to Design Compiler and DesignWare.

    I want to evaluate half-precision floating pointer multiply-accumulator. So I decided to use DW_fp_mac (verilog) in DesignWare Library.

    However, there are some errors while compiling.


    Code:
      Beginning Pass 1 Mapping
      ------------------------
      Processing 'DW_fp_mac_inst'
    
    Statistics for case statements in always block at line 457 in file
    	'./DW_fp_mac__rtl.v.e'
    ===============================================
    |           Line           |  full/ parallel  |
    ===============================================
    |           145            |    auto/auto     |
    ===============================================
    Error: *** Generation of expr Fanout_18[8:0]=I1+I2;Fanout_198:00]=I3+127;Fanu_28[[8::0]={C0,C}?0:Fannout_1;Faoouut_29[8:0]={C,C3}?0:Fano_9nu_66[8888::0]={C45}?FFaanouutt_29:Fanoutt__28;Fanout_27[8:0]={C4}Fu_2annoutt__29;11777==FFaannoouut_28<Fanout_29;O11155[8:0]=Fanout_26+2O6[8:0]=Fnuuttt__26-Fanout_27 failed.
    Fatal: Internal system error, cannot recover.
    
    Release = 'E-2010.12-SP2'  Architecture = 'amd64'  Program = 'dc_shell'
    Exec = '/scale/cal/opt/synopsys/design_compiler/amd64/syn/bin/common_shell_exec'
    .


    Below is my .tcl file. I use OSU(Oklahoma State University) FreePDK 45nm as standard cell library.
    Version of Design Compiler is E-2010.12-SP2 for amd64
    Version of DesignWare is E-2010.12-DWBB_201012.2.



    Code:
    #/**************************************************/
    #/* Compile Script for Synopsys                    */
    #/*                                                */
    #/* dc_shell-t -f compile_dc.tcl                   */
    #/*                                                */
    #/* OSU FreePDK 45nm                               */
    #/**************************************************/
    
    
    #/* All verilog files, separated by spaces         */
    set my_verilog_files [list ./verilog_files/DW_fp_mac_inst.v ]
    
    #/* Top-level Module                               */
    #set my_toplevel adder
    set my_toplevel DW_fp_mac_inst
    
    
    #/**************************************************/
    #/* No modifications needed below                  */
    #/**************************************************/
    set OSU_FREEPDK [format "%s%s"  [getenv "PDK_DIR"] "/osu_soc/lib/files"]
    set search_path [concat  $search_path $OSU_FREEPDK]
    set alib_library_analysis_path $OSU_FREEPDK
    
    set synthetic_library [list dw_foundation.sldb]
    set link_library [set target_library [concat  [list gscl45nm.db] [list dw_foundation.sldb]]]
    set target_library "gscl45nm.db"
    define_design_lib WORK -path ./WORK
    set verilogout_show_unconnected_pins "true"
    
    analyze -f verilog $my_verilog_files
    
    elaborate $my_toplevel
    
    current_design $my_toplevel
    
    link
    uniquify
    
    
    set_driving_cell  -lib_cell INVX1  [all_inputs]
    
    compile
    
    check_design
    report_constraint -all_violators
    
    set filename [format "%s%s"  $my_toplevel "_syn.v"]
    write -f verilog -output ./output/200/$filename
    
    set filename [format "%s%s"  $my_toplevel "_syn.sdc"]
    write_sdc ./output/200/$filename
    
    set filename [format "%s%s"  $my_toplevel "._syn.sdf"]
    write_sdf ./output/200/$filename
    
    set filename [format "%s%s"  $my_toplevel ".db"]
    write -f db -hier -output ./output/200/$filename -xg_force_db
    
    
    redirect ./output/200/timing.rep { report_timing }
    redirect ./output/200/cell.rep { report_cell }
    redirect ./output/200/power.rep { report_power }

    Actually, I want to input clock and reset, but remove it for simplicity.


    DW_fp_mac_inst.v is as below. It's same as given example.


    Code:
    module DW_fp_mac_inst( inst_a, inst_b, inst_c, inst_rnd, z_inst, status_inst );
    
    parameter inst_sig_width = 23;
    parameter inst_exp_width = 8;
    parameter inst_ieee_compliance = 0;
    
    input [inst_sig_width+inst_exp_width : 0] inst_a;
    input [inst_sig_width+inst_exp_width : 0] inst_b;
    input [inst_sig_width+inst_exp_width : 0] inst_c;
    input [2 : 0] inst_rnd;
    output [inst_sig_width+inst_exp_width : 0] z_inst;
    output [7 : 0] status_inst;
    
        // Instance of DW_fp_mac
        DW_fp_mac #(inst_sig_width, inst_exp_width, inst_ieee_compliance) U1 (
          .a(inst_a),
          .b(inst_b),
          .c(inst_c),
          .rnd(inst_rnd),
          .z(z_inst),
          .status(status_inst) );
    
    endmodule
    Is it any problem in my .tcl file? I'm not sure that it's okay to use OSU freePDK.
    I got correct report when I execute with my own verilog file (fixed-point MAC).
    If you know what is the error, please let me know. There is no related writing in google.


    Or if there is a easier way to evaluate half-precision floating point MAC of DesignWare Library using Design Compiler, please let me know.





    The other way I tried is

    I got all of related verilog files and change name of modules.

    dffr.v, DW_fp_dp2.v , DW_fp_ifp_conv.v, DW_fp_mac.v, DW_ifp_addsub.v, DW_ifp_fp_conv.v, DW_ifp_mult.v, ,half_prec_mac_DW.v

    However, I found that given verilog files from DW is not synthesizable. For example, they use === and !== (I edited it) and use while (I can't edit it). So I give up to synthesize these files.

    •   AltAdvertisment

        
       

  2. #2
    Advanced Member level 5
    Points: 7,493, Level: 20

    Join Date
    Apr 2016
    Posts
    1,584
    Helped
    275 / 275
    Points
    7,493
    Level
    20

    Re: Help to synthesize floating point MAC in Design Compiler using DesignWare library

    Your TCL has no bearing on what is happening here. This looks like a bug with the DW library.
    Really, I am not Sam.



    •   AltAdvertisment

        
       

  3. #3
    Newbie level 2
    Points: 26, Level: 1

    Join Date
    Feb 2019
    Posts
    2
    Helped
    0 / 0
    Points
    26
    Level
    1

    Re: Help to synthesize floating point MAC in Design Compiler using DesignWare library

    Thanks for your reply!

    You mean that I have to re-install my DW library? I'm wondering that there is any problem in the way I use OSU FreePDK 45nm.



    •   AltAdvertisment

        
       

  4. #4
    Advanced Member level 5
    Points: 7,493, Level: 20

    Join Date
    Apr 2016
    Posts
    1,584
    Helped
    275 / 275
    Points
    7,493
    Level
    20

    Re: Help to synthesize floating point MAC in Design Compiler using DesignWare library

    Quote Originally Posted by DreamCaCao View Post
    Thanks for your reply!

    You mean that I have to re-install my DW library? I'm wondering that there is any problem in the way I use OSU FreePDK 45nm.
    DW is library independent. Your library choice cannot break it. I think this is a DW bug that you stumbled upon, but I can't prove it.
    Really, I am not Sam.


    1 members found this post helpful.

  5. #5
    Newbie level 3
    Points: 391, Level: 4

    Join Date
    Feb 2017
    Posts
    4
    Helped
    0 / 0
    Points
    391
    Level
    4

    Re: Help to synthesize floating point MAC in Design Compiler using DesignWare library

    You might want to see if you have access to a newer version of the dc_shell tool as the one you are using is nearly 8+ years old. Can you confirm the dates of the DW library you are using and the tool version?



--[[ ]]--