Enorize
Newbie level 4
Hey,
I'm newbie to cadence, and I have final project on cadence a,d exam is in 5 days, and I'm still stuck at this error that prevent me from finishign my final circuit, I use premade transistor layout and capacitors, so when I generate my circuit i got this error, and I don't know hot to solve it at all: n+sd to psub spacing must be <=10um, so please I'm begging you all, help me, I have no one and this is my last ressort.
P.s: I'm using cadence virtuoso v5
I'm newbie to cadence, and I have final project on cadence a,d exam is in 5 days, and I'm still stuck at this error that prevent me from finishign my final circuit, I use premade transistor layout and capacitors, so when I generate my circuit i got this error, and I don't know hot to solve it at all: n+sd to psub spacing must be <=10um, so please I'm begging you all, help me, I have no one and this is my last ressort.
P.s: I'm using cadence virtuoso v5