Need of default unique case item in State machines encoding using enum types

I am using system verilog to code a state-machine.
I defined the state variables using enum types...

typedef enum logic [1:0] {A, B, C} state_t;
state_t curr_state, next_state;

I am using the "unique case" statement for coding the combo block

always_comb
begin
unique case (curr_state)
A: ---------
B: ---------
C: ---------
endcase
end

Do I need to specify "default" statement? How simulation and synthesis tool behaves by using/not using "default" in this scenario?

How tool (synthesis/simulation) behaves differently with the following combinations with respect to "default" statement
1) enum types and unique case
2) Constant parameter declarations and unique case
3) enum types and case (without unique)
4) constant parameter declarations and case (without unique)


Thanks,
Ashish

Short answer, it depends on the tool. Modern synthesis tools are usually recoding state machine states during the logic optimization process. If your tool does this, there's a good chance that 1) - 4) end up with the same gate level logic. To achieve a specific state machine encoding, you'll use vendor specific synthesis attributes. Review your tool manual.

FvM said:

Short answer, it depends on the tool. Modern synthesis tools are usually recoding state machine states during the logic optimization process. If your tool does this, there's a good chance that 1) - 4) end up with the same gate level logic. To achieve a specific state machine encoding, you'll use vendor specific synthesis attributes. Review your tool manual.

Click to expand...

Hi FvM,

I am mostly interested to know, will tool create latches for the code I mentioned?
I am using 2 bit logic to define 3 states using "enum". And using "unique case" statement without "default".

If you worry about latches generated for next_state, put a default assignment in front of the case structure. A superfluous default case would neither do any harm.

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Ultimately, if you want to know how your RTL is synthesized, review the gate level net list.

FvM said:

If you worry about latches generated for next_state, put a default assignment in front of the case structure. A superfluous default case would neither do any harm.

Click to expand...

I do know that "default case" will not harm. But wanted to know that if we don't put any default case then what is intended from "unique case" and "enum types"? Do they make any difference to the tool?
It is obvious that different tool may behave differently but there must be some intention to introduce the "unique" and "enum" keyword in the language.

So first I would like to know the intention of "unqiue case" and "enum types" without default statement (only 3 states are defined) and then I can look at the particular tool's behavior.
From intention I mean weather it should create latch or not?

I'm not aware of an effect of unique key word in synthesis. In simulation, violations are generated for not matched case values. Enum is a means of abstraction, it doesn't change the behavior of the underlying type, usually int or bit/logic vector.