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Metastable signal ANDed with logic 0

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Ashish Agrawal

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Hi,

I have an 2 input AND gate. Let's say inputs to AND gate are I1 and I2; output is Y.

I1 is coming out of a negedge triggered flop whose clock is I2. If I make sure I1 is settled within half cycle of I2. Is it okay to AND both the signals?
The time, I1 is metastable, I2 is Logic 0; So Y will be logic 0. Is this understanding right?

To summarize the query, what should be the output of an AND gate when one input is meta-stable and other input is logic 0 ?

Thanks,
Ashish
 

I think this should be fine, as long as you can ensure that I2 is low until I1 is stable. BUT, you have to consider routing delays. If I2 arrives at the AND gate later than the output of the FF, you could get a glitch. Personally, I would look at changing my design. Maybe take the output of the FF and connect it to another FF that is clocked by the rising edge of I2. Then your routing tools will (hopefully) take care of the timing.
 
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