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adjusting output common mode voltage

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bharat_tangudu

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I am trying to design the fully differential opamp. I put all the values according to mathematical calculation and put those values in simulator. After some simulation, some transistors are going to linear again against the calculations. I found a very high value of common mode voltage at output node. I tried all the means to get all MOSFETs into saturation. But i was not able. Can somebody suggest how to make these into saturation and setting output commonmode voltage to VDD/2

I am attaching the schematics
1.png

2.png
 

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