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  1. #1
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    Difference between n well drawing and n well pin layers in cadence virtuoso layoutXL

    I am drawing a layout of an inverter in cadence virtuoso layout XL. The problem is there are two layers visible in P MOS one is n well draw and other one is n well pin. and by default it (n well pin) is showing connection to VDD. As a result of this when I tried to connect the out, it is showing short circuit with vdd. I dont know how to solve this issue ? Please someone xplain me as soon as possible .

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  2. #2
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    Re: Difference between n well drawing and n well pin layers in cadence virtuoso layou

    Hi hetira,

    If in your schematic the PMOS Source(S) of the inverter is connected to VDD then it should be fine.

    Normally NWell is tied to positive potential which is VDD then it is not short circuit it is intended.

    Cheers,

    fixrouter


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  3. #3
    Newbie level 6
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    Re: Difference between n well drawing and n well pin layers in cadence virtuoso layou

    thanks fixrouter u solved my problem



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