How to design a frequency adjustable NCO?

I'm trying to implement a digital PLL to track a certain frequency. And I need to implement a NCO in it.

I learned there're 2 ways to do that.
1. Using IPcore to generate a NCO
or
2. Using a counter as phase accumulator(with fixed step size increment) and a LUT as sine table.

The above 2 methods can only generate a fixed frequency NCO. But I need the NCO's frequency to vary a little bit, from time to time, to track the incoming sine wave.

Since the phase might not always increase at a fixed step, do I need to use cordic method to generate the sine/cosine wave?

NCO frequency is variable by varying the phase increment. Frequency resolution is only limited by the accumulator word width. See https://en.wikipedia.org/wiki/Numerically_controlled_oscillator

LUT method is suitable for many NCO applications, using e.g. 8 to 12 bit phase resolution. If available memory is low, you can use fewer points with linear interpolation.

I didn't get the NCO fundamentals straight...should've done more research before asking
Thanks.

Hi,

For an NCO you don´t need a LUT. (nor for a PLL)

For an NCO a counter as phase accumulator and some "overrun detection" is all you need.
NCO means numeric controlled oscillator ... this says that you may change the frequency....

The benefit of an NCO against a "divider" circuit is that the NCO is able to generate frequencies in equal steps.
(Whereas the divider has good resolution at low output frequencies only, but poor resolution at high output frequencies)

What exactely do you mean with "incoming sine wave"?
This sounds like an anlog signal. Usually you want to proceess digital data.
How do you form it into digital? (ADC? comparator)
And how do you decide to "track" it? (comparator, XOR...)

The whole application depends a lot from your incoming signal (frequency, jitter...) and what´s your expected performance.
You need to specify a lot.

Klaus

Incoming sine wave seems to refer to an "all-digital PLL" with sinusoidal reference input. You find it e.g. in grid tied inverters or other power electronic systems with active front end. This designs typically use a sine LUT and digital sine signals.

incoming sine wave is already digitized. To track it, I intend to use a all-digital PLL, which consists of a phase comparator(a multiplier), a loop filter and a NCO.

Earlier I was confused with the concept "equal steps", or "fixed phase increment". Now I see it's not necessarily a fixed phase increment --- the phase increment could vary so that NCO could catch up with the incoming digitized sine wave.

Using LUT, the address corresponds to the frequency... so adding 1 each system clock generates a sine wave with the frequency of "system frequency / 2^N", adding 2 each system clock merely doubles the generated sine wave frequency.
The more accumulator word widths we use, the finer the frequency becomes. But there could always be some residual frequency error left, due to the fact that LUT address only accepts integer increment.

That's how I understand it...correct me if anything is wrong...thanks.

Hi,

Using LUT, the address corresponds to the frequency...

Click to expand...

the NCO frequency is determined by the phase_increment_value (and other fixed factors)

Therefore I think you don´t need a LUT.
If phase_increment_value = 0 then NCO_frequency = 0
If phase_increment_value = N then NCO_frequency = N x freq_step_size. Linear relationship.

Klaus