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latches irregularity and modelsim&signaltap result didn't agree

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bravoegg

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the code in modelsim simlulation turns out to be different from signaltap waveform.

the idea is to set x to a certain value and keep it, when some condition is met.
like when wren_s == 1, then set x = 3 and keep it, unless another if-statement gets invoked.
Code: 
always@(*)begin
    if(!rst_n)
        x = 0;
    else if(wren_s)
        x = 3;  //1 + 1 + 1
    else if(se_s)
        x = 6; //1 + 1 + 3 + 1
    else if(read_s || pp_s)
        x = 262;    //1 + 1 + 3 + 256 + 1
    else
        x = x;
end

if_2.png

modelsim simulation works excalty as I wanted, but the real signaltap waveform is different.
In signaltap waveform, when the if-statement condition is met, x is set to predefined value(which is what I want), but the circuit didn't keep the value, instead immediately change x's value to 262. Why would x be latched to 262?

Where did I get it wrong? Please help...Thanks in advance.


if_1.png

if_3.png
 
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You don't show read _s or pp_s in chipscope. I assume they are set to 1.

But this brings up another question, why are you using latches? There are no latches in an FPGA and have to be created with luts. They are prone to timing problems and will react to glitches on any signal. I highly recommend you do not use a latch.
 

I have used Signaltap to make sure that read_s and pp_s only become 1 when the corresponding state is activated, and they're 0 in the range of the graph posted above.

It's a bad practice and I later used a sequential logic and avoided the problem. But I want to figure out why x be latched to 262, even when read_s and pp_s are 0?
 

are you sure they havent glitched and high for a period shorter than the system clock?
Did you check the technology map view to check the circuit was as you expected?

I dont trust behaviour of latches ever. So I never use them.
 
maybe there's glitch...I'll just take this as a lesson and avoid using latches again.

I couldn't understand the technology map, they're like klingon language to me...

Mr, I assum you're an advenced developer..do you guys often check the technology map?
 

bravoegg said:
maybe there's glitch...I'll just take this as a lesson and avoid using latches again.

I couldn't understand the technology map, they're like klingon language to me...

Mr, I assum you're an advenced developer..do you guys often check the technology map?
Click to expand...

Usually not - if you follow good design practice (synchronous circuits) then the design should just work as simulated.
Ill use it to ensure a design has used DSP/RAM registers when I expect it to, and use it to check number of logic levels between registers to check timing. But generally I dont check it, because thats a massive thing to look at when your design has 200k luts and 200k registers...
 
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