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interview Q of verilog/vhdl

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abhineet22

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.implement a 2x1 mux using a 1x2 decoder

please send me the link
of these question
 

2x1 mux is a universal gate

some interview questions -

1. What is difference between signal and variable ?
2. How to write FSM in Moore/Mealy style ?
3. About sensitivity list for combinational amd sequential circuit
4.Design a COMBINATIONAL circuit that can divide the clock frequency by 2. write vhdl code...
6.Implement 3x8 decoder using 1x2 decoders..
7. Design a clock that will half the input frequency using only combinational logic ckt...
8..Implement 4 input OR gate using 2X1 mux...
9.Draw logic ckt for 4-bit Binary to Reflected code....
10.F=ab+cd+ef implement using 2 input NAND gates only........
11..Prove that 2x1 mux work as Universal logic gate..
12.Design a ckt that will devide a clock 3/2 with 50% duty cycle..
 

vhdl code for 3x8 decoder

barkha said:
some interview questions -

1. What is difference between signal and variable ?
2. How to write FSM in Moore/Mealy style ?
3. About sensitivity list for combinational amd sequential circuit
4.Design a COMBINATIONAL circuit that can divide the clock frequency by 2. write vhdl code...
6.Implement 3x8 decoder using 1x2 decoders..
7. Design a clock that will half the input frequency using only combinational logic ckt...
8..Implement 4 input OR gate using 2X1 mux...
9.Draw logic ckt for 4-bit Binary to Reflected code....
10.F=ab+cd+ef implement using 2 input NAND gates only........
11..Prove that 2x1 mux work as Universal logic gate..
12.Design a ckt that will devide a clock 3/2 with 50% duty cycle..
Click to expand...
can any one provide the answers of these questions too???
 

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