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Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 module pwm(clock,switches,pwm); parameter sd = 195;//step delay in pulse input clock; input [7:0]switches; output pwm; reg pwm; reg [15:0] counter=0; always@(posedge clock) begin counter=counter+1; if(counter<=switches*sd) pwm=1; else pwm=0; if(counter>=50000) counter=0; end; endmodule