gstekboy
Member level 5
The below diagram is the parallel MAC structure.
In parallel MAC both partial product addition and accumulation take place at same time.
I want to multiply 5 and 3.(both are 8 bits)
The 4 partial product I got from modified booth are
p1: 0000 0101
p2: 0000 1010
p3: 0000 0000
p4: 0000 0000
I cross checked above value to below partial product addition+accumulation stage of MAC structure.
but it is not delivering 15 (0000 1111) as output.
what happened? is there any wrong ?
The entire IEEE paper is given below for reference.
View attachment 05337888_2.pdf
Thanks.
In parallel MAC both partial product addition and accumulation take place at same time.
I want to multiply 5 and 3.(both are 8 bits)
The 4 partial product I got from modified booth are
p1: 0000 0101
p2: 0000 1010
p3: 0000 0000
p4: 0000 0000
I cross checked above value to below partial product addition+accumulation stage of MAC structure.
but it is not delivering 15 (0000 1111) as output.
what happened? is there any wrong ?
The entire IEEE paper is given below for reference.
View attachment 05337888_2.pdf
Thanks.