[SOLVED] Parallel MAC unit design problems.[Need help]

[gstekboy]

The below diagram is the parallel MAC structure.
In parallel MAC both partial product addition and accumulation take place at same time.


I want to multiply 5 and 3.(both are 8 bits)
The 4 partial product I got from modified booth are
p1: 0000 0101
p2: 0000 1010
p3: 0000 0000
p4: 0000 0000

I cross checked above value to below partial product addition+accumulation stage of MAC structure.


but it is not delivering 15 (0000 1111) as output.
what happened? is there any wrong ?

The entire IEEE paper is given below for reference.
View attachment 05337888_2.pdf

Thanks.

 

[ads-ee]

what happened?

Don't know, you didn't supply anything that would allow someone to help. Hence the 100+ views and no answers.

is there any wrong ?

Yes, you have an error somewhere in you implementation.

 

[gstekboy]

Don't know, you didn't supply anything that would allow someone to help. Hence the 100+ views and no answers.

Yes, you have an error somewhere in you implementation.

Thanks for your reply.
The partial products are the output of booth encoder.The partial products are given as input to partial product addition+accumulation stage.But not giving me correct output while cross checking.
This paper is already implemented and published in IEEE, so I think the partial products generated may be wrong in my case :bang::bang::bang:.

What partial products I need to give input to get correct output (00001111)?

 

[D.A.(Tony)Stewart]

Detail how you implemented and differences from expected.

As we know a simple adder is an XOR gate 1(+)1=0 with a carry bit=1

 

[gstekboy]

Detail how you implemented and differences from expected.

As we know a simple adder is an XOR gate 1(+)1=0 with a carry bit=1

Based on the theory of modified booth encoder .
I multipled 5 and 3.(both are 8 bits)
The 4 partial products got as per theory are given below.
p1: 0000 0101
p2: 0000 1010
p3: 0000 0000
p4: 0000 0000


I give the generated 4 partial products to input of 'partial product addition+accumulation' stage of MAC structure.
But not giving me output of 15(00001111).

 

[D.A.(Tony)Stewart]

So what u get? Do you use any sim tools for analytics?

details details...

of course
1010(+)
0101=
1111

try other inputs what , how is it defined in software? Hardware? Generated?

 

[ads-ee]

You still aren't giving us any useful information to help you. Like the code you wrote for the 'partial product addition+accumulation', which is where you have a problem. Are we supposed to read your mind and see where you made a mistake? If you don't have code then you could show us how you compute the output maybe someone will spot a mistake in your calculation.

Actually, I don't expect you to actually supply any information as that seems to be a trend in your posts (I reviewed all 41 of them). Even the ones where you supply an "answer" can be relegated to the useless information pile.

 

[gstekboy]

Please close the thread, started a new discussion in stackexchange.

https://electronics.stackexchange.c...el-mac-unit-based-on-modified-booth-algorithm

 

[D.A.(Tony)Stewart]

Please close the thread, started a new discussion in stackexchange.

https://electronics.stackexchange.c...el-mac-unit-based-on-modified-booth-algorithm

Wishing you luck... Show what you tried... for better luck

 

[gstekboy]

Based on the theory of modified booth encoder .
I multipled 5(0101) and 3(0011).(taken as 4 bits)
The 4 partial products got as per theory are given below.
p0: 11111011
p1: 00010100
p2: 00000000
p3: 00000000
Adding above bits got answer as 00001111 (15)