Who can give me a list of file extentions used in synopsys ASIC design flow?

for example, for xilinx FPGAs I say this:
*.v -> Synthesis -> *.edf
then *.edf and *.edn and *.ncf and *.ucf -> ngdbuild -> *.ngd
*.ngd -> map -> *.ncd
*.ncd and *.pcf -> par -> *.ncd

I want a same diagram for synosys ASIC design flow. Who can help?