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Eagle PCB design - Clearance errors

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TokTok

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Hi all,

I'm designing a wireless relay card using eagle and I'm encountering clearance issues as indicated in the attached diagram.

Clearance.png

I've been through the following sites to understand the clearance and its issues or errors:
**broken link removed**
http://en.wikibooks.org/wiki/Practical_Electronics/PCB_Layout
http://frontdoor.biz/HowToPCB/HowToPCB-Trace&Space.html
http://designinthetrenches.com/pcb-design/
https://www.edaboard.com/threads/240437/

I also read through and ran the DRC command (http://web.mit.edu/xavid/arch/i386_rhel4/help/42.htm) and its results indicated the clearance issues I have.

Below are the schematic and board files:
Schematic - http://sites.google.com/site/bgedsadownloads/EASYDAQ-XBEE.sch?attredirects=0&d=1
Board - http://sites.google.com/site/bgedsadownloads/EASYDAQ-XBEE.brd?attredirects=0&d=1

My grid settings are as below:
Size: - 1mm.
Multiple - 1
Alt: 0.025 inch
Display: on.
Style: lines.

Apologies if my questions sounds basic I'm still new to eagle, how can I get rid of this clearance problem.

Thanks.
 

Looks to me like R20 has a dead short.

Capture4.PNG

Did you mean to switch layers?

John
 

Hi Alex,

It's hard to say what the other errors are, as they don't show in what you posted. If it is not a very big or complex board you can zip the sch and brd files and attach them here. The reason we need the schematic is that there may be some traces that are not connected to pins. Did you have any "overlap" problems too? If you are sensitive about posting the sch file, then just post the brd file (zipped). It will be much easier to help you with that available.

John
 

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