Verilog-a with Tunnel Fet

// VerilogA for ptmBasic, PTFET, veriloga

`include "constants.vams"
`include "disciplines.vams"

module PTFET(d,g,s);
inout d,g,s;
electrical g,d,s, dd, ss;
real Ids, Cgs, Cgd, Qgs, Qgd, f;
real VgsEff;
integer out_file;
parameter real W=1;

analog begin

// We assume that the PTFET and NTFET drive currents are similar
Ids=$table_model(-V(dd,ss), (-V(g,ss)), "/mnt/cnm/jnunez/cadence/PTM/TFET/IdVg-GaSb-InAs-HNTFET-Lg-20nm.tbl","1LL,1LL");
// We do not assume that the PTFET and NTFET gate capacitances are similar because the hole and electon DoS in InAs are significantly different
Cgd=$table_model(V(dd,ss), (V(g,ss)), "/mnt/cnm/jnunez/cadence/PTM/TFET/CGD-GaSb-InAs-HPTFET-Lg-20nm.tbl","1LL,1LL");
Cgs=$table_model(V(dd,ss), (V(g,ss)), "/mnt/cnm/jnunez/cadence/PTM/TFET/CGS-GaSb-InAs-HPTFET-Lg-20nm.tbl","1LL,1LL");

if(analysis("dc")) begin
I(dd,ss) <+ -1*Ids*W;
V(dd,d) <+ I(dd,ss)*55/W;
V(s,ss) <+ I(dd,ss)*55/W;
end
else begin
if(analysis("tran")) begin
Qgd = (W*1*Cgd)*(V(g,dd));
Qgs = (W*1*Cgs)*(V(g,ss));
I(dd,ss) <+ -1*Ids*W;
I(g,dd) <+ ddt(Qgd);
I(g,ss) <+ ddt(Qgs);
V(dd,d) <+ (1/(W*0.1e-15))*ddt(V(d))*55/W;
V(ss,s) <+ (1/(W*0.1e-15))*ddt(V(s))*55/W;
end
end



end
endmodule

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