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yep, its high price is a big problem anyway!
However, it can perfectly fit with the trend of high-speed and low-power design.
The market, not designers, always decides everything.
The problem with SOI is the process cost and Process Integration issues. Every time it appears to be cost competative, something in CMOS breaks the mould. Since SOI has been available for 20+ years, ask yourself why it is not mainstream IC processing - answer: it is not easy, not cost competative and does not keep pace with CMOS IC processing.
It does have a future in high voltage ICs, but for mainstream stuff - back a different horse.
I can tell you .... it costs alot
developing, for example, 90nm technology in SOI is very different than that in bulk in terms of tecbhnology and mass production issue.
just list some problems here in SOI
heat dissipation, thermal budget issue, silicon film thickness variation.... alot alot
unless it is really a need.. I still believe bulk technology still the mainstream even go to 65nm or 45nm
jason_class, you are really putting effort to know more about SOI. Goodluck!
I believe the answers from previous members since December 2004 until the most recent one should have already convinced you about SOI cost and substrate quality by now.
I wonder if the IBM paper published by Dr Ning is helpful to you.
If you want to know more about SOI, try to search with ADDITIONAL keywords like Strained Silicon, SiGe, BiCMOS. You might get more leads to wider knowledge.
Thank you so much.
I have tried to look up all info in this forum on soi cmos.
I will check the IBM paper you mentioned.
By the way Scottieman, I saw from books and papers that soi cmos is compatible with bulk cmos integration. What do you mean by the process issue?
Kindly enligthen
Thank you so much.
I have tried to look up all info in this forum on soi cmos.
I will check the IBM paper you mentioned.
By the way Scottieman, I saw from books and papers that soi cmos is compatible with bulk cmos integration. What do you mean by the process issue?
Kindly enligthen
SOI is perfectly CMOS compatible, it doesn't mean that you no need to fine-tune your process
The major challenge I mentioned before is focusing on the techology node around 65nm.
Give you one exmaple here to illustrate my point
If you want to fabricate a 65nm channel length SOI MOSFET, you may need to thin down the SOI film around 100nm or even lower to supress the short-channel effect. By doing it, you probably introduce SOI film thickness variation during the prcoess. If you fine down prcoess is fine tune to 5nm error, you already introduce 5% error in SOI thickness. Moreover, ifyou want to put SOI in mass production (e.g. 8 inch wafer), can you ensure 5% error across the entire wafer? How about if we want to do it in 12inch wafer (300mm).......then will know making single transistor is totally different then a circuit (I remember this sentence came from Intel).
SOI is both Bipolar and CMOS Compatible. But making Bipolar compatible CMOS is not easy, especially on the same SOI.
scottieman, nanometre gate like 90 and 65 nm have the problem with geometries, that limit transistors matching used in analog (not to even mention RF), electromigration (causing short-circuit between adjacent interconnects and open-circuit in single interconnect), difficulty in deep-sub vertical interconnects etc.
It is an overall problems to other processes, not just SOI alone.
The problem concerning the silicon fil uniformiti only arises in fully depleted as Vth of transistors operating under this regime depends on silicon thickness. Also some special care must be take when chosing the implant energies as the distribution cernter of the implanted ions must lay at the center of the active silicon. Actually, thinner than 100nm silicon layers are needed ~50nm.
On the other hand, partially depleted devices are much less sensitive to silicon thickness variations.
That is why, current SOI processes are using PD devices, but FD soi is coming up.
On the other hand, short channel effects are easier to control in SOI than in bulk.
The problem concerning the silicon fil uniformiti only arises in fully depleted as Vth of transistors operating under this regime depends on silicon thickness. Also some special care must be take when chosing the implant energies as the distribution cernter of the implanted ions must lay at the center of the active silicon. Actually, thinner than 100nm silicon layers are needed ~50nm.
On the other hand, partially depleted devices are much less sensitive to silicon thickness variations.
That is why, current SOI processes are using PD devices, but FD soi is coming up.
On the other hand, short channel effects are easier to control in SOI than in bulk.
Just a supplement here
Although PD is good in terms of process variation, PD also introduce floating-body effect, which makes the MOS transistor in SOI technology has memory effect. In other words, the transistos's characteristic depends on previous state.
For FD SOI, it is easier to control short-channel effects than in bulk silicon. But there are double well and even triple well bulk silicon, which is used to counter such effects, so effective that the results are much better than PD SOI. With downscaling of supply voltage Vdd respective to downscaling of gate length, L, short-channel effect like threshold variation is better controlled.
But in one thing mind, short-channel effects like hot-carrier effect due to hot-carrier impact and ionisation cannot be solved (at the moment) in both bulk silicon and SOI.
Thank you so much for writing back with so many opinions to share.
I know from book that PD SOI's Vth is independent of back gate bias due to its large neutral region in the silicon active film. However FD SOI will have large vaiation in its Vth due to process variation(as what has been brought up on the issue of thin film uniformity on 8 or even 12 inch wafers).
Anyone knows if the implant energy and dosage for SOI cmos should be lower or higher compare to bulk cmos?
I often found from internet that the soi cmos is often associated with strained soi cmos. Does it mean current state-of-art is using soley strained Si-Ge even for soi cmos(both FD SOI and PD SOI)?
Hear that all the integration method such as Ldd and STI .. applied in bulk cmos can be used to fabricate cmos soi. But any general changes must be made?
May I know if current soi cmos still use locos or already replaced by STI?
If anyone knows which paper described best about soi cmos and bulk or even strained cmos, kindly let me know the title.
From books, I know that there are accumulation and inversion mode for cmos device. Do you know which type is more preferred for nmos and pmos in design or fabrication point of view?
Thank you for your help and advice in advanced
I sincerely hope we can discuss about the above topics
Hear that all the integration method such as Ldd and STI .. applied in bulk cmos can be used to fabricate cmos soi. But any general changes must be made?
You have a lot of questions
Let me answer part of your questions, and let other memebers here to help you.
LDD in nowadays nano-technology is no longer exist.
LDD is originally developed to solve the hot-carrier effect, as the supply voltage (Vdd) is scaling with the technology, hot carrier effect is not that serious compared with sub-micron technology.
Instead of LDD, source/drain extension (SDE) is used. SDE is mainly used to minimize the short-channel effect without a great trade off in source/drain resistance.
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