horzonbluz
Full Member level 4
constant(1)
Hi, my friends. When i run DFT, it reports there are two clock gating cell have constant 1 value output.
Usually in the test condition, the test_se signal will and the Clock signal, that is to say test_se && clock. Why the report said the clock gating cell has constant 1 value?
I don't know how to handle this problem. Who can help me and give me some advice?
Hi, my friends. When i run DFT, it reports there are two clock gating cell have constant 1 value output.
Usually in the test condition, the test_se signal will and the Clock signal, that is to say test_se && clock. Why the report said the clock gating cell has constant 1 value?
I don't know how to handle this problem. Who can help me and give me some advice?