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SYNOPSYS DC & CADENCE NCLAUNCH

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NATHANHSIEH

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nclaunch

HI!!
I used synopsys design compiler to generate gate level file .
how to used cadence nclaunch( or ncverilog) simulation????
pre-sim is easy but synthesised gate level simulation need to link database or
lib.If you have any method let me more clear the sense...
 

cuvmur

hi,
for your synthesis, you need synthesis library named with .db.
so your simulation tool need a simulation library also. it's a file with .v or a directory that all file(cell) with .v.
you would use '-v' or '-y' option.
 

ncelab: *e,cuvmur:

HI~z81203
Do you use "GUI(grapher user interface)" for dc & ncverilog???
Your means ".v" is after synthesize gate level's ".v" file???
When I run synthesized simulation(the tool is cadence nclaunch),that
appear error message is
" ncelab: *E .CUVMUR:instance of module/UDP 'XOR2MAC' is unresolved
in 'worklib.lab1_DW01_add_9_0:module' "
If you know this error please help me .....
 

nclaunch simulation

Nope, all you needed is verilog simulation model. This model are provided by library vendor and usually in two formats:

1. A single .v file includes all cell instances.
2. A directory contains a lot of .v, in which all the cell has their only .v file associated with.

You should run your gate level simulation with this library included.
 

nclaunch gate level simulation

ye
Before doing ncelab, you should compile the cell model file in ncvlog or ncverilog, such as tsmc25.v.
 

nclaunch cadence

Simple way Just use ncverilog in command line mode

ncxlmode netlist.v -v tsmc25.v

where netlist.v <-- ur netlist to be simulated
tsmc25.v <-- cell library verilog models you can change this with ur
U need to place both the file in same dir or use +incdir+ option.
 

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