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$ynplify ASIC vs. Design C0mpiler

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linuxluo said:
... When I resynthesis, I use the source file and wlm above to generate optimized netlist , and again sta and p&r until timing closure.
Is it true?
Thanks.
Click to expand...
Not source file, IPO is to optimize your placed design, so you must export the netlist after placement and CTGen, but because of the interconnection and loading may be different as DC estimated, so you have to adjust(insert/delete/resize) the drive strenth of your driver source of the nets, that's exactly the resynthesis does, that's why resynthesis needs custom ILM(or SDF) files from placement.
So after resynthesis, the netlist changed from the last placed netlist, you have to do ECO placement again, repeat this IPO iteration until all timing are closure.
 

Hi, CatKing
As you said, I use netlist and sdf generated from place&ctg tools to resynthesis. But what does synthesis tool do with them? just optimizing?
optimizing for drc ? timing?
You know ,now I am confused . So can you tell me in detail?
By the way ,Is it necessary to use netlist and sdf generated by route to resynthesis?
Thank you very much.
 

Sure it's optimize for timing.
To optimiza the routed netlist is a good idea, because the ILM is the real cases. but it can not work, because after the re-optimizing and ECO P&R, the ILM changed because the routing have some change. so it's almost have the same accuracy as the estimated ILM of placement, but both of them are better than DC's wireload estimation.
 

Hi, CatKing
In your context, does ILM equal to WLM (wire load model)? What's it?
 

Sorry, i made a misatke inthe prev post, it should be WLM, not ILM(Interface Logic Models).
ILM can make DC/PT/PhysOpt run faster with less memory.
To check the detail info, see the doc: Introduction to Physical Compiler and ILM Flow
 

Check FPGA Compiler as well...
I think it is nice
 

Happy on $ynplify asiC

I am using $ynplify Asic for Asic tape outs.

The last tape out I was involved with I did with
Alliance. That was a challence, that I only were able to
fullfill cause I normaly do analog stuff and do not full LVS
on the complete design.

I thing I never and ever will try D.A.

GwarCad
 

FPGA compiler is for FPGA whereas DC and $yn@sic is for ASIC
 

I like new tool

I ever use DA/DC but synopsys is "old tool or old algrithm" and I am use
synplicity ASIC .. My friend use magama , another friend Co use Ambit , because We need "cheap" solution ..
and Synopsys "NOT" it is too expensive for designer / design house ..
If we only design small Chip We don' need DC ..
 

I want to ask a question that is it possible fo rme to convert using synopsys DC into Synplify ASIC,
if the answaer is yes, what about convert the DesignWare component??

i have try using Synplify-ASIC, and read the manual, but it doesn't mention any about Designware component, what should i do??

thanks a lot

reagrds,
aramis
 

1.) Generate for each Designware component a gate level netlist, with Synopsys DC.
2.) Remove all Designware components modules from Synplify ASIC project, and declare them Black Boxes
3.) Use multiple EDIFs for Place&Route

gab
 

DW can be outputed as netlist, so it will be ok if you use the same library.
Please correct me if i miss any points.
thx.

aramis said:
I want to ask a question that is it possible fo rme to convert using synopsys DC into Synplify ASIC,
if the answaer is yes, what about convert the DesignWare component??

i have try using Synplify-ASIC, and read the manual, but it doesn't mention any about Designware component, what should i do??

thanks a lot

reagrds,
aramis
Click to expand...
 

>aramis wrote:
>I want to ask a question that is it
>possible fo rme to convert using
>synopsys DC into Synplify ASIC,
>if the answaer is yes, what about
>convert the DesignWare component??

>i have try using Synplify-ASIC, and
>read the manual, but it doesn't
>mention any about Designware
>component, what should i do??

>thanks a lot

>reagrds,
>aramis

use the tools 'lib2syn.exe' to convert
*.lib->*.syn, *.sel
also you can translate the sy*sys
constrain file
then you can do the synthesis

BR,
Ejean
 

..

Maybe it is also very difficoult to convert many fixed (by post experience) DC-sh or DC-tcl scripts to S.ASIC-like scripts.
 

From my experience, DC perform the synthesis job better than ambit. Anyone agree with me ?

Btw, most of the foundry's design kit have full support of DC and little support of ambit, but no support of Synplify ASIC.
 

I have tried the both tools .

I feel the DC is more trustable and reliable . However if your company have more resource, it's worth to tape-out some test chips with synplify.
The reason is 2 folds , one is that the synplify got much easy and fast to get the netlist , the other is that it have been the most powerful fpga compiler , if you are doing verification and debug on fpga then transfer it to asic . I have tried the verplex for comparason of asic and fpga netlist . It's perfect if you use the same eda vendor tools , otherwise you would have some naming trouble or case's dont care assign mismatch in verplex .
As for the synopsys .lib translation problem . It's always a problem and even worse is that synopsys lib parser change from one version to another version giving the compability issue between old and new version . If you watch some unusual "conditional timing arc" or "power pad bi-direction" used in your .lib , it had better doing some manual modification before translate it to syn .
 

I USED SYN DC 2003.3 & SYNplify A$IC 3.04 recently for compiling one of my module. With DC I used .35um library & a very basic script
Speed < 20Mhz
Area 4k gates
SUN machine --compile time 45 min

with synplify I used TSMC .13u lib

speed 73MHZ
area 30kgates
AMD 2500+xp 512mb --compile time 30min

I didnt understand why such high area with A$ic.......Any comments
 

It look like some arithmetic units in your module .
The serial/parallel architecture implementation plus array/bus instantiation can result in significant gate count/speed difference.
 

Nobody said:
It look like some arithmetic units in your module .
The serial/parallel architecture implementation plus array/bus instantiation can result in significant gate count/speed difference.
Click to expand...

Yeah my module was FFT/IFFT block.. I didnt understand what u said . can u please explain?

tnx
whizkid
 

How maturly can the free tool, Alliance, be used in taping out a chip .. and what is the average threthold of a chip size that we should not go beyond, in order to ustilize this tool and get the best of it ..
anyone has a real taping out expereince with Alliance ?
 

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