alexhugo
Junior Member level 3
How can we meet timing ("SLACK MET") and have none zero "DESIGN RULE COST" together?
Hi,
I am synthesizing a circuit (using DC) and I see that the timing is met (SLACK MET) by using report_timing. The problem is that "DESIGN RULE COST" is not zero. As far as I know none zero design rule cost means that the timing is not met.
What am I making wrong? How is possible to have these two together?
Thanks
Alex
Hi,
I am synthesizing a circuit (using DC) and I see that the timing is met (SLACK MET) by using report_timing. The problem is that "DESIGN RULE COST" is not zero. As far as I know none zero design rule cost means that the timing is not met.
What am I making wrong? How is possible to have these two together?
Thanks
Alex
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