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    Designing CIC for delta sigma modulator

    Hi all!

    I am trying to design a simple CIC decimation filter for my first order delta sigma modulator. Oversampling is 1024 and output is 1 bit. I tried to go with the standard theory for design. It gives 11 bits for 1st integrator, and 21 for the next. I am amazed over the fact that how can a 21 bit output be obtained when the modulator itself does not have such a high resolution? I mean... the modulator resolution itself is less than 12 bit. How can one extract a 21 bit output?

    Please clarify. I am suspecting that some of the bit patterns at the output may be random in such a case.

    Thanks in advance!

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    Re: Designing CIC for delta sigma modulator

    For a better understanding of your design, you should tell the full specification of your CIC decimator. The width of individual integrator stages is commanded by the output width, CIC order and decimation factor. It doesn't necessarily imply that all bits are significant. Some bits may be also omitted by applying Hogenauer's pruning theory.

    I don't think, that insignificant CIC bits are random. They'll rather show patterns depending on the input sequence. But for a randomly varied input, they can be expected to be randomized as well.


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    Re: Designing CIC for delta sigma modulator

    Delta sigma modulation gains resolution by averaging many coarse samples. It's similar to averaging a noisy signal to increase the signal to noise ratio. The more samples you average, the better the signal to noise and thus the better the resolution.
    Zapper
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    Re: Designing CIC for delta sigma modulator

    Quote Originally Posted by FvM View Post
    For a better understanding of your design, you should tell the full specification of your CIC decimator. The width of individual integrator stages is commanded by the output width, CIC order and decimation factor. It doesn't necessarily imply that all bits are significant. Some bits may be also omitted by applying Hogenauer's pruning theory.

    I don't think, that insignificant CIC bits are random. They'll rather show patterns depending on the input sequence. But for a randomly varied input, they can be expected to be randomized as well.
    Thanks FvM. Sorry I was out for the weekend so couldn't reply. Here it goes.
    I wish to have a CIC for a DSM with OSR = 1024, bandwidth 500 Hz, first order, single bit. I planned a second order CIC, but the no. of output bits seem to be rising beyond the DSM resolution. Please help me understand this. Let me know if some more info is reqd.

    thanks,
    dushyant.

    ---------- Post added at 07:22 ---------- Previous post was at 07:20 ----------

    Quote Originally Posted by crutschow View Post
    Delta sigma modulation gains resolution by averaging many coarse samples. It's similar to averaging a noisy signal to increase the signal to noise ratio. The more samples you average, the better the signal to noise and thus the better the resolution.
    Thanks crutschow for the reply. So the no. of averaging bits are fixed here. 1024. Now, it should still not give such a high resolution. bit puzzled...



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    Re: Designing CIC for delta sigma modulator

    You didn't tell the number of output bits.



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    Re: Designing CIC for delta sigma modulator

    Quote Originally Posted by FvM View Post
    You didn't tell the number of output bits.
    Thanks. So here you go.
    For a 1024 OSR, output freq is 500 Hz, and each integrator needs bit increment of 10 bits. So input bits is 1, after first integrator it goes to 11, second one gives 21 bit output. And this goes through differentiators to get a 21 bit output. I am surprised because the DSM itself does not have such a high resolution output.

    Hope it clarified my question.

    thanks for your interest.
    dushyant.



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    Re: Designing CIC for delta sigma modulator

    For a 1024 OSR, output freq is 500 Hz, and each integrator needs bit increment of 10 bits. So input bits is 1, after first integrator it goes to 11, second one gives 21 bit output.
    No, that's not correct. Actually the first integrator needs the maximum bit width, the succeeding integrators and comb stages can possibly have a reduced width according to pruning calculations. I suggest to review Hogenauers original paper or some other CIC literature.

    I get e.g. these parameters for a 16 Bit output second order CIC. The additional output bit is provided for rounding purposes.

    Code:
    -- Stage   1 INTEGRATOR. Bit width :  21 
    -- Stage   2 INTEGRATOR. Bit width :  21 
    -- Stage   1 COMB.       Bit width :  18 
    -- Stage   2 COMB.       Bit width :  17
    P.S.: An edaboard member reminded me to this previous thread https://www.edaboard.com/thread127067.html
    Last edited by FvM; 27th March 2012 at 16:40.


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    Re: Designing CIC for delta sigma modulator

    Quote Originally Posted by FvM View Post
    No, that's not correct. Actually the first integrator needs the maximum bit width, the succeeding integrators and comb stages can possibly have a reduced width according to pruning calculations. I suggest to review Hogenauers original paper or some other CIC literature.

    I get e.g. these parameters for a 16 Bit output second order CIC. The additional output bit is provided for rounding purposes.

    Code:
    -- Stage   1 INTEGRATOR. Bit width :  21 
    -- Stage   2 INTEGRATOR. Bit width :  21 
    -- Stage   1 COMB.       Bit width :  18 
    -- Stage   2 COMB.       Bit width :  17
    P.S.: An edaboard member reminded me to this previous thread https://www.edaboard.com/thread127067.html
    Thats nice FvM. Thanks for the practical information.
    Could you tell me how you reduced the bits from the second stage to the third and fourth ones? IS there some mathematics involved?



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    Re: Designing CIC for delta sigma modulator

    Could you tell me how you reduced the bits from the second stage to the third and fourth ones? IS there some mathematics involved?
    Yes, there's "some mathematics involved" and it's not very easy. It's exactly derived in Hogenauer's original paper and briefly described in U. Meyer-Baese DSP with FPGA. There'a simple formula for the bitwidth of the first integrator and a more complex calculation how to reduce it towards the output.


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    Re: Designing CIC for delta sigma modulator

    Ok...got it. Thank you so much FvM. Took me some time to do all the literature study and understand your comments.

    One more question. For a second order modulator, there are two integrators. Each integrator with above mentioned oversampling should give rise of 10 bits. How can we have first two integrators of 21 bits, both? I am asking because I saw this at various other implementations also.

    Awaiting response.
    juneja



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    Re: Designing CIC for delta sigma modulator

    Hogenauer is giving this mathematical explanation for it:
    Not only is Bmax the MSB at the filter output, but it is also the MSB of all stages of the filter. This can be shown by applying modulo arithmetic to the filter output function. For two's complement arithmetic, the modulo operation can be implemented by simply eliminating bit positions above Bmax.

    Since the modulo operation is used at the filter output, the same modulo operation can be applied independently to each integrator and comb stage. This implies that Bmax is an upper bound for each filter stage.

    It is now shown that Bmax is also a lower bound. Since the first N stages of the filter are integrators with unity feedback, it is apparent that the variance of the integrators outputs grow without bound for uncorrelated input data. As seen at the output register, Bmax is the MSB for each integrator since this as a significant bit and is the highest order bit that can propagate into the output register. Since a propagation path must be provided through the comb section for this MSB, it can be be concluded the Bmax must be the MSB not only for the integrators, but also for the combs that follow.


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    Re: Designing CIC for delta sigma modulator

    Thanks a lot FvM.

    That clarified much of my doubts. So here is the program I made for that. Its implemented on a 32 bit machine. So output is kept to be 32 bits. oversampling is kept to be 64 only right now for debugging. The problem is that the code is working, but giving strange outputs. Could you please help me with this? I am taking inputs by changing the value of variable "in" in the code. A constant zero value for "in" means minimum input to the modulator. The corresponding value at the output should hence be all zeroes. Similarly, a constant "1" for in corresponds to highest inputs, and should give a high on all pins (I suppose). The outputs I am getting, however, are like this:
    Code:
    For in=0: comb2=0x0000 0000; (correct to expectations)
    For in=1: comb2=0x0000 1000; (expected 0xFFFF FFFF instead)
    I tried to toggle value of "in" at every run, to emulate the sigma delta output for zero input. Output for that was 0x0000 0800. I could not comprehend its correctness. Can you kindly help me? It would be really a favor, since this is the thing blocking my degree.

    The code follows next:
    Code:
    while(1)
    {
    	for (n1=0;n1<64;n1++)
    		{
    		//if (in==1)
    		//{in=0;}
    		//else 
    		//{in=1;}
    		
    		//First integrator
    		integrator1=integrator1+in;										// y(n)=x(n)+y(n-1)
    		integrator2=integrator2+integrator1;							// z(n)=y(n)+z(n-1)
    	    } // end for
    
    // Start low speed operations here.
    		comb1=integrator2-last_integrator2;									// First differentiation
    													// v(n)=z(n)+z(n-1)'+1
    													// First differentiation over
    
    		comb2=comb1-last_comb1;									// w(n)=v(n)+v(n-1)'+1
    													// Second differentiation over
    		last_integrator2=integrator2;
    		last_comb1=comb1;
    }



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    Re: Designing CIC for delta sigma modulator

    Your test is different form the original scenario in several regards.
    - OSR of 64 iinsteas of 1024
    - no truncation to the correct bitwidth
    - numbers should be interpreted as two's complement

    To understand the transfer function of the implemented filter, you should vary the average value of in continuosly over the range 0..1

    P.S.:
    To add a simple point. The OSR can be understood as a gain factor. So a second order CIC with OSR=64 has a gain of 64^2. When using an unsigned number representation, and no additional carry presets, input values 0 and 1 are mapped to 4096 (0x1000) and 0 respectively. Having additional bits above the MSB isn't a problem, it's sufficient to cut them at the output.

    The classical CIC scheme introduced by Hogenauer uses signed number representation and some special tricks with carry bits to map the input data to the intended output number range without saturaton logic. If you want to reproduce it exactly, you need to study Hogenauers original paper.

    Or use your own number representaion, e.g. unsigned as in your test. Then you should evaluate the it's behavior in a test.
    Last edited by FvM; 21st April 2012 at 09:55.



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