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memory design in verilog

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priyanka24

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i want to design dual port RAM. here is the code i have written.


module mem (r_wb,addr,d,q);
input r_wb;
input [3:0] addr;
input [3:0] d;
output [3:0] q;
reg [7:0] q;
reg [3:0] mem_bank [0:7];
always @(r_wb)
if (r_wb) #15 q=mem_bank[addr];
else #15 mem_bank[addr]=d;
always @(addr)
if (r_wb) #15 q=mem_bank[addr];
else #15 mem_bank[addr]=d;
always @(d)
if (r_wb) #15 q=mem_bank[addr];
else # 15 mem_bank[addr]=d;
endmodule

I want to know how if i want to read and write contents in this memory then how to do it.. plz help me...
 

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