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Gate Level Simulation: Delay or No Delay?

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When you use Verilog for full chip gate-level simulation, do you use delay on standard cell library? Why? Do you use delay on the test program? When do and when do not? Why?
 

Delays are required on IP/RTL models involved in gate-level sims. These Verilog #delays insert required routing delays on actual (hardware) paths.
 

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