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Missing lockup latches in the design

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manikumar1207

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Hi,

After synthesis we scan stitch the design using DFT compiler. DFT compiler inserts lockup latches for the signals crossing the domain. Is there any way to check whether the inserted lockup latches are sufficient or if any of them is missed out. Please suggest me a way to do it.


Thanks in Advance ,
Mani
 

Report the scan order and set false path between all the clock domains.
Report the timing on every flop to flop path in the chain and if anything comes up as unconstraint, it's where a lockup latch is missing.
 

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