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Hello,
I run LVS in Calibre Interactive, but encountered an error relating to ERC error. The error covers the area of PMOS layout (in the attached file).
Please help me how to fix this error.
Thanks
It's not easy to understand the error description w/o layer definition... But pay attention on common issues:
1) connect all gates (as i understand from the layout there are some floating.
2) the second error looks like you've got nmos surrounded by nwell ring w/o psub contact inside.
Please go ahead to your command file for LVS check and find details.
Pls search ERC1063 in command file.
Some notes can be found.
If you still have problem, pls post some segments about ERC1063 in the command file.
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