trouble simulating a possible tri state buffer

dear forum members,

here's the code i'm currently simulating:

module tsbuf (dataout, data, datain, rw);
input [15:0] dataout; // data out from the CPU
inout [15:0] data; // data in from the outside to the CPU
output [15:0] datain; // external bidirectional bus
input rw; // 1 indicates read

assign data = rw ? 16'bz : dataout;
assign datain = data;
endmodule

and here's the testbench i've written for the same:

module tsbuf (dataout, data, datain, rw);
input [15:0] dataout; // data out from the CPU
inout [15:0] data; // data in from the outside to the CPU
output [15:0] datain; // external bidirectional bus
input rw; // 1 indicates read

assign data = rw ? 16'bz : dataout;
assign datain = data;
endmodule

When rw = 1, the behaviour is as expected i.e, datain is driven by data. However when rw = 0, data, which acts as output port in this case is not driving dataout.

thanks for your help in advance,
Sumanth

How did you connected these modules in your test bench?

Syswip said:

How did you connected these modules in your test bench?

Click to expand...

Sorry..... i didn't copy the testbench right. here it is :

module tsbuf_tb;
reg [15:0] r_dataout;
wire [15:0] w_data;
wire [15:0] w_datain;
reg r_rw;
reg [15:0] r_data;
parameter ten_ns=10;

tsbuf ts1(r_dataout, w_data, w_datain, r_rw);

assign w_data = r_rw ? r_data: w_data ;

initial
begin
r_rw = 1;
r_data = 16'hbbbb;
r_dataout = 16'haaaa;
#(ten_ns) r_rw = 0;
#(ten_ns * 10) $finish;
end

endmodule

I'm just testing tsbuf as of now.

Of course it will not work.
You must assign Z state to the w_data when it is output from your module.

assign w_data = r_rw ? r_data: {16{1'bz}} ;

Syswip said:

Of course it will not work.
You must assign Z state to the w_data when it is output from your module.

assign w_data = r_rw ? r_data: {16{1'bz}} ;

Click to expand...

Thanks a lot. Now, its working.