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MIPS code in verilog HDL

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sarah23

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can nyone tell me abt simple MIPS verilog code without pipeling ...n its implementation on fpga
 

check this out!

h**p://inst.eecs.berkeley.edu/~cs61c/fa04/hw/proj3/proj3.pdf
 

thanx its really helping alot..!
 

i hav got this MIPS code but when i synthesize this on Xilinx ise10.1 it give 0 eroors but alot of warnings abt ports that r not connected but i think all of perfectly connected ...can nybody figure it out where z the problem ...code is attached with it
 

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  • mips_single.zip
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