cheenu2002
Junior Member level 2
Hi,
I have tried to design a folded cascode. The schematic and AC response are attached with this mail. I have 2 questions:
1. The PhaseMargin is very poor. Can you help me to understand how to
improve PM . Is it bcoz I havnt connected load cap (Cl)?
2. I am able to easily bias the transistors if I use a pmos current mirror load.
But if I use a current source load, then either qp31,29 or qn14,12 goes into
linear region. I am not able to get how to bias the folded cascode with the
current source load. Is there any technique that I should follow. Can anyone
pls help me.
I have tried to design a folded cascode. The schematic and AC response are attached with this mail. I have 2 questions:
1. The PhaseMargin is very poor. Can you help me to understand how to
improve PM . Is it bcoz I havnt connected load cap (Cl)?
2. I am able to easily bias the transistors if I use a pmos current mirror load.
But if I use a current source load, then either qp31,29 or qn14,12 goes into
linear region. I am not able to get how to bias the folded cascode with the
current source load. Is there any technique that I should follow. Can anyone
pls help me.