verimark
Newbie level 1
simulation of verilog netlists
Hi all. I am new in this area and not that familiar with the design flow and the CAD tools. Can someone please just point me in the right direction as to what I need to do in order to simulate a synthesized (with Synopsys) Verilog netlist in Cadence with hSpice or Spectre? I need to perform a transient analysis.
The Verilog netlist has component names (such as muxes and flip-flops) that seem to be library specific. Do I have to supply a library file to Cadence as well?
I really appreciate your help.
Hi all. I am new in this area and not that familiar with the design flow and the CAD tools. Can someone please just point me in the right direction as to what I need to do in order to simulate a synthesized (with Synopsys) Verilog netlist in Cadence with hSpice or Spectre? I need to perform a transient analysis.
The Verilog netlist has component names (such as muxes and flip-flops) that seem to be library specific. Do I have to supply a library file to Cadence as well?
I really appreciate your help.
