gepo
Newbie level 6
gate level of register
Hi, all
I found a weird problem.
I have a register level verilog file mips.v and a gate level verilog file mips_struct.v which is generated by design compiler of synopsys. A testbench file: mips_test.v
however when I conduct the simulation of mips.v using modelsim. The result is right.
However, when i used the same testbench and the gate level file: mips_struct.v to do the simulation using modelsim. The result is totally different.
Any ideas?
Thanks
Added after 4 minutes:
whethere there is some verification tool to verify different level desings?
Thanks
Hi, all
I found a weird problem.
I have a register level verilog file mips.v and a gate level verilog file mips_struct.v which is generated by design compiler of synopsys. A testbench file: mips_test.v
however when I conduct the simulation of mips.v using modelsim. The result is right.
However, when i used the same testbench and the gate level file: mips_struct.v to do the simulation using modelsim. The result is totally different.
Any ideas?
Thanks
Added after 4 minutes:
whethere there is some verification tool to verify different level desings?
Thanks