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    asic design flow

    please send me asic design flow and fpga design flow

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  2. #2
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    Re: please send me asic design flow and fpga design flow




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  3. #3
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    Re: please send me asic design flow and fpga design flow

    asic flow: RTL coding-> RTL simulation-> synthesis->dft insert->formal->STA->gate simulation->backend flow



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    Re: please send me asic design flow and fpga design flow

    Quote Originally Posted by ljxpjpjljx View Post
    asic flow: RTL coding-> RTL simulation-> synthesis->dft insert->formal->STA->gate simulation->backend flow
    It means DFT is before LEC(formal verification)????

    What is the meaning of gate simulation???



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    Re: please send me asic design flow and fpga design flow

    is ASIC design from quartet is the same with that from synopsis

    Quote Originally Posted by pmat View Post



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