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  1. 25th October 2008, 09:50 #1
    adilkhan123
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    asic design flow

    please send me asic design flow and fpga design flow
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  2. 26th October 2008, 07:57 #2
    pmat
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    Re: please send me asic design flow and fpga design flow

    Hi,
    ASIC Flow:
    http://www.quartetdigital.ca/asic_flow2.shtml
    FPGA Flow:
    http://www.quartetdigital.ca/fpga_flow2.shtml

    Pavlos

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  3. 27th October 2008, 03:25 #3
    ljxpjpjljx
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    Re: please send me asic design flow and fpga design flow

    asic flow: RTL coding-> RTL simulation-> synthesis->dft insert->formal->STA->gate simulation->backend flow

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  4. 7th June 2013, 05:11 #4
    amitk3553
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    Re: please send me asic design flow and fpga design flow

    Quote Originally Posted by ljxpjpjljx View Post
    asic flow: RTL coding-> RTL simulation-> synthesis->dft insert->formal->STA->gate simulation->backend flow
    It means DFT is before LEC(formal verification)????

    What is the meaning of gate simulation???

  5. 8th June 2013, 15:45 #5
    onion2014
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    Re: please send me asic design flow and fpga design flow

    is ASIC design from quartet is the same with that from synopsis

    Quote Originally Posted by pmat View Post
    Hi,
    ASIC Flow:
    http://www.quartetdigital.ca/asic_flow2.shtml
    FPGA Flow:
    http://www.quartetdigital.ca/fpga_flow2.shtml

    Pavlos

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