Normal collection of cell used as spare cell

Hello everyone,

Can anyone share their methodology of choosing collection of cell
which used as spare cell module?

For example spare module:
DFF - 2
NAND - 3
NOR - 3
INV - 2

Can you share yours?.

Thanks in advance.

Hi,

Actually the sparecells that you need to insert in your design will come from the top level designer. But if not then you can insert sparecells equal to 2% of your total design cells. And regarding to the
sparecell list, you can include the cells as per the max number of the types used in your design.
You should use, buffers and inverters, flipflops, muxes, and universal gates in a sufficient amount, so that any functionality can be formed with that and if any timing violations then you can use either buffers or inverters.

It may help you.

Thanks..

HAK..

Hello hiral.kotak,

I would like to hear more from you on your comment "..if any timing violations then you can use either buffers or inverters". Do you mean to say, we should insert the bufferes and inverters of different size(drive strength /gain)?


Now a days multi Vt designs are made... In spare cells we should have cells with multi Vt ? I think we should.... any one has any hands on on this ?

One more thing I would like to know is regarding the location of the spare cells... where these spare cells kept on chip... I mean is there any guideline for that...? Should we keep sparecell block in center of 4 blocks ... or some thing like that so when we have to do ECO at metal level , that perticular block of space cell can be used to repair the fault for any of 4 blocks...? Any Idea on this ?

One more question... do we keep space cells block in our RTL itself or we insert it ater Placement only i.e. at RTL level is is not present .. it is invited at placement stage only??

Thank you ...

can any one share their view?
I'm specifically interested in spare cells at RTL level,

Hi,

For the question regarding the use of multi vt for spare cells, as per my knowledge you can include them in the list so as per the design requirement i.e. either power(high vt for less leakage) or timing critical (low vt cell for less delay)you can choose the multivt cells for spare cells.
Regarding the placement of the spare cells, the pnr tool will distribute them all over the chip area if you specified automatic sparecell insertion or if you want the spare cells near some logic or some block specifically then you can define a window (x y width height) of that region and can add spare cells in that region.
For the sparecells inserted from RTL, as per me, spare cells can be inserted in RTL also or they can be inserted at a later stage i.e. after placement stage. It is better to add them after placement stage as all the stdcells will be placed and legalized after placement so sparecell wont affect their placement or in some cases if you have inserted spare cells before placement then also pnr tool will give priority to the functional cell placement and then place the sparecells accordingly.

It may help you.

Thanks..

HAK..