Jifeng.Cui
Newbie level 3
As we all know, the wire delay would contribute more to path delay as technologies shrink down, such as 45nm node. But how to evaluate it before real design? I know we could layout small circuit to see the delay percentage, if we want to compare the wire delay in two technologies, such as 90nm and 45nm, what can we do to reflect the real case, like, the circuit topology(what circuit)? drive strength, wire level (how many metal layers we use in this example) and the wire length.........
Do anyone have suggestions? OR any prior work that I can reference to?
Do anyone have suggestions? OR any prior work that I can reference to?