how to estimate the logic cell from c-code

Hi all guys,

I have a c-code program and wanna map it into FPGA. Now I'm assigned to estimate this c-code program need how many logic cells and memory of FPGA roughly. Would you please give me some advice? How to begin? Or is there any tool which can convert c-code to verilog-code and send out a report for hardware consumption? Thanks.

--BR
--Trashbox

You should think about CLK first of all.
I mean what is your phisical clk in the FPGA?
After that you need to reason if you need to count some times in your code if yes you need a counter long such as you can count the time you need (and you'll know how much ff you need because you know clock).
After that reason in terms of inputs and outputs and think of use 1 ff for each one of them (count them).
Ok now think about your C code in terms of states and count them (each states count 1 ff).
Then sum up your input and output register and multiply them by the stage, sums the result up with your stage you've your more or less final count.

That could be a sort of rule of thumbs for a "simple" project with only 1 thread.
Remember that VHDL is concurrent whileas C isn't.
If your code has a lot of maths you need to estimate how many bits you need to to rapresent the numbers, moreover you can take in account if the FPGA has DPS block that you can use or memory also.

It's not so simple and it's very specific to your code, I hope that you've written your code thinking that it will be for an FPGA.

Another count you need to do is if you need some fifo in order that your data input and output are consistent with your way of read/write them.
Example if you've a micro that need to read something with a DMA and so with a burst, you need to pack your data in a fifo and use a signal to tell the micro that data are ready.

I can still continue for a lot of time/example, it's too code specific in order to help you, sorry.

I hope at least to have given you an idea.