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Oscillations at a phase margin of 90?

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Another question:

What is the frequency of the oscillations in comparison to the gain crossover resp. the phase crossover frequency ? Is it much higher ?
 

I think we're starting to converge here. The loop's oscillation frequency is close to the phase cross over point, close to 1 MHz!! But why would it oscillate if its stable with enough phase and gain margins?

Here is an asymptotic sketch of the loop's response.
 

Well, the BODE response looks rather normal - although for high frequencies .....? Not satisfying.

But again there is another question - just to verify the loop gain:

The max. loop gain (60 dB) has to be equal to the max. opamp gain multiplied by the gain of the MOSFET-stage (load dependent) and multiplied by a constant factor of the voltage divider (normally 0.5) driving the pos. opamp input. Have you done this calculation by hand ?
 

You're right about the Bode plot behavior at high frequency, I don't like it either.

What do you mean by the hand calculations of the loop gain? Do you mean does the simulated gain match that which I've hand calculated?? Well its quite close, specially at this loading point...

I know its a small gain :D
 

Do you mean does the simulated gain match that which I've hand calculated?? Well its quite close, specially at this loading point...

Yes, that´s what I was asking.
 

If the oscillation appears after appling a monopulse (like that in the topic I made), I advice you to find the loop gain and phase at different current loads.(sweep the load current and monitor the loop gain and phase)
 

What do you mean by applying a monopulse? These oscillations appear without any perturbation to the circuit :|

I've done a load sweep to check the phase margin across loads and it was inconclusive; it seems always stable

quaternion said:
If the oscillation appears after appling a monopulse (like that in the topic I made), I advice you to find the loop gain and phase at different current loads.(sweep the load current and monitor the loop gain and phase)
Click to expand...
 

elmolla said:
What do you mean by applying a monopulse? These oscillations appear without any perturbation to the circuit :|

I've done a load sweep to check the phase margin across loads and it was inconclusive; it seems always stable
Click to expand...

what does that mean... the phase margins are always the same or its just that u have safe margins...

coz in former case you can doubt the sim results...
 

Hi elmolla,

by the way - did you do already something against the oscillations (independent on the weird loop gain results) ?
Up to now we didn´t speak about the output compensation capacitor and its real part.
Can you give some information on this ?
 

It changes, but I'm still in the safe region

ashish_chauhan said:
elmolla said:
What do you mean by applying a monopulse? These oscillations appear without any perturbation to the circuit :|

I've done a load sweep to check the phase margin across loads and it was inconclusive; it seems always stable
Click to expand...

what does that mean... the phase margins are always the same or its just that u have safe margins...

coz in former case you can doubt the sim results...
Click to expand...

Added after 3 minutes:

Yes, I've done some adjustments to the design and its working now :D, but I'm still pursuing this problem because no one knows when it'ld happen again if we don't know the cause.

What do you mean by the output compensation capacitor real part?

LvW said:
Hi elmolla,

by the way - did you do already something against the oscillations (independent on the weird loop gain results) ?
Up to now we didn´t speak about the output compensation capacitor and its real part.
Can you give some information on this ?
Click to expand...
 

probably he is refering to the "esr"

can you tell what exactly did you do as a modification?
 

I had to redesign the amplifier giving it more drive capability
 

ashish_chauhan said:
probably he is refering to the "esr"
can you tell what exactly did you do as a modification?
Click to expand...

Yes, for stabilty reasons it makes sense (very often it is necessary) to put a resistance in series to the output capacitor ; sometimes it is sufficient intentionally to use for this purpose a "bad" capacitor with a low Q value (i.e. a prety high esr = equivalent series resistor).
 

Yeah, I got what you're talking about.

I tried increasing the ESR but it was in vain.

I didn't use the ESR from the begining because I though why should I add the ESR, to get a zero for more stability, if the phase margin is already 90.
 

If you are designing on chip cap ldo then you shouldn't use esr.

It is used for off chip cap ldo.

For off chip cap ldo : large esr gives larger spikes while smaller esr degrades PM.

It seems that you are designing on chip cap ldo ?

about the amplifier : did you try class AB second stage?
 

A Class AB second stage would be great, but its power consumption would be large I guess, this'ld increase the LDO's quiescent current, right?
 

quaternion said:
If you are designing on chip cap ldo then you shouldn't use esr.

It is used for off chip cap ldo.

For off chip cap ldo : large esr gives larger spikes while smaller esr degrades PM.

It seems that you are designing on chip cap ldo ?

about the amplifier : did you try class AB second stage?
Click to expand...

Are'nt you using an off chip cap?

and as for esr in offchip case it won't neccesarily degrade the pm... depends on how you are trying to compesate the loop.
 

ashish_chauhan said:
quaternion said:
If you are designing on chip cap ldo then you shouldn't use esr.

It is used for off chip cap ldo.

For off chip cap ldo : large esr gives larger spikes while smaller esr degrades PM.

It seems that you are designing on chip cap ldo ?

about the amplifier : did you try class AB second stage?
Click to expand...

Are'nt you using an off chip cap?

and as for esr in offchip case it won't neccesarily degrade the pm... depends on how you are trying to compesate the loop.
Click to expand...

I don't know to whom you are directing these words, but I agree that it isn't necessary to compensate off chip cap ldo with esr ,(I know that it has large variability ).
 

why not post you testbench and the simulatio result
 

The test bench is a simple RC load and the input it a fixed DC voltage with enough headroom for LDO operation.
 

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