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What is Verification Plan and Test Plan.........?

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kushagrak

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Hi All,

can any body help me in understanding the difference between Verification Plan and Test Plan.........?


Thanks in Advance

KUSHAGRA
 

Basically there is no difference between these two ....... Both are refered to same thing.

Some people might say verification plan as overall SOC verification plan and test plan as tests written for how to verify each feature of SOC/ chip.

But both are for plan created for verification of a SOC/module.
 

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    kushagrak

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I am expecting some more answers.............can any one.......
 

Basically, they means the same thing. Just different word(Verification and test).

Verification Plan: It is generate by
-reading the spec
-extracting function
-extracting rule
-create "checker"
-create "functional coverage"
-...

You must list all things about verification. Let others know how you verify DUT. And after you verify, you can guarantee DUT is clear.
 

verification plan is the function point of DUT you want to verify , usually function coverage will do so!
 

will the verification plan same for every project or will it differs from one project to other......
 

Verification plan is written after reading the specs of design i.e what are the features ur design has and how are u going to verify those features.

Verification for different projects will be different assuming they have different functionality or features.

If they have some features same then u can use that part of verification plan to verify those features for both projects.
 

But I think Verification plan is for whole system verification and Test Plan is for specific tests just like FIFO , Registers , Path and all.we can say that testplans are subset of Verification plan
 

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