Transient analysis & other questions on diff amp

I have a simple double ended output diff pair
- vdd = 2.5V, vss = 0
- small gain (Av = 2)
- input transistors (m1 & m2)= nmos
- load transistors (m3 & m4) = diode-connected pmos
- min input common mode, vic(min) = 0.8V
- nmos (M5) tail current = 100uA

operating points ok, ac plot ok (almost 0 db). having some problems with transient analysis

I set the following config to the ins & outs:
dc=1V + 1mV sine wave to 1st input
dc=1V + 1mV sine wave (180 out of phase) to 2nd input
CL = 2pF to both output ends

What i got is
- input ok (1mV sine wave at dc level =1V)
- output 2mV sine wave but at dc level 1.455V

I got a few questions
1) did i set the testbench correctly? offset is large 0.455V? if I omit the dc=1V, all transistors will be in cut-off (except m5). what did i do wrong? since the gain is almost unity, shouldn't the dc offset be very small?

2) is it possible to set vic(min) to be 0V? i did that but then i got vds(sat) of M5 to be -ve.

3) if i set vic(min) close to 0V, I will get vds5(sat) -ve value in my calculation. [Vic(min) = Vds5(sat) + Vgs1]. any other to do this? is there any rule of thumb on the appropriate icmr for a given vdd to vss range (in this case, 0 to 2.5V vdd)?

4) if i want to use pmos as the input transistors, how to determine W/L of M5. I used Vic(min) = Vds5(sat) - Vtp. I couldn't get M5 to be in saturation no matter what vic(min) I used.

sorry for the long text. eager to learn. may have more questions.

TQ

1- The 1.45V is the output common mode, it's not a dc offset. This voltage is the drop from the supply caused by the Vgs of the diode connected loads. You can adjust this value by adjusting both W and L of the load devices.

2- For the architecture you chose, you can't set Vic to 0V because you need Vt of the diff pair devices+Veff of active devices+veff of the current mirror NMOS. If you use a PMOS diff pair and use a small resistor load, you may be able to able Vic near to 0V. There're also topologies used that can get rail to rail input using 2 input pairs, one NMOS pair and another PMOS pair, but they would complicate your design.

3- same as 2

4- You should note that to achieve common mode rejection, if you use PMOS input pair, you current mirror should also be PMOS connected to the supply (not NMOS connected to ground as your current design).

Tq 4 the answers. Really helpful. I got a few more questions.

- It is said that the above diff pair consumes voltage headroom? What does it mean?

- I'm designing another diff pair, this time the load is PMOS current source with biasing Vb (Razavi, fig 4.32(b)). Input transistors are still NMOS. The diff amp has 2 output ends. Design specs: Vdd=2.5V, Vss=0V, current sink Iss = 100uA and gain Av=100. I got (W/L) of load = 1.5 from vic(max)=2V. I know that W/L of input is calculated from gain=gm(in)*ro(load)//ro(in). How to determine the ro value?

TQ.