tinytseng
Newbie level 6
ddr2 timing question
I am doing a ddr2 sdram controller now.
how can I make the data written to the ddr2 sdram change every one half clock with its changing 90 degree before the dqs edge(just use verilog)?
I am doing a ddr2 sdram controller now.
how can I make the data written to the ddr2 sdram change every one half clock with its changing 90 degree before the dqs edge(just use verilog)?