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synthesis problem on Design Compiler

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design compiler synthesis

when synthesis , I write design into mydesign.v

compile -scan

But I found lots of scan enable of scan D-flip-flop were connected to 1'b0,
Anyone can tell me how to solve it ?
 

There are lot of reasons for connecting to logic zero. If you can share your DC script, we can analyze.

one reason i could think about it is your settings .

If you are setting set_auto_disable_drc_nets -constant to false (the default
is true), DC adds tie off cells . If you set the variable to false before your initial compile -scan, then Design Compiler connects the scan enable pin of every scan flop to a zero..


Best of luck..

Regards,
Sam
 

Hi,

when you use the compile -scan in the synthesis the ordenary flops where converted to the scan flops inorder to not to chage the functional behaviour of u r design the SCAN_ENABLE pin of SCAN FLOPS wher connetced to the 1'b0.which will enable u r d pin to go onto the Q when u apply the clk.after the scan sticth was over the SCAN_ENABLE pins of these flops will be connected to the scan_enable net of the design.

regards,
ramesh.s
 

I think compile -scan , just to change DFF to scan-DFF, it doesn't insert scan chain, so scan-dff connect to 1'b0. you should use other command to insert scan chain.
 

i think during synthesis step it just replaces every FF with Scan FF and scan enable is tied to '0'. During DFT,i .e with insert_dft it stiches all scan FF and now scan enable can be controlled from toplevel input.
 

compile -scan as said is just a dft preveiw command. Its not a final command for inserting scan chains. It replaces the FFs with scan FFs to be able to do a more accurate timing. It is to consider the impact of those FFs on timing.
It is usually followed by 'insert_scan'/'insert_dft' command to complete the mapping or 'scan_enables'.
Kr,
Avi
http://www.vlsiip.com
 

As many people mentioned, compile -scan will just replace Flip flops in design with scan flops. Scan_enable is connected to 1'b0 to make sure that functionality is not affected. Also Scan_in is connected to output pins Q of same flop.
While Scan stitching scan_enable is connected to actual scan_enable pins and Scan_in is connected to Q of some other flop in chain.
 

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