Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
to help you in understanding how fan in fan out influences designs take in consideration an example. Consider a driver loaded by N gates (N is the desired fan out), each one with input Capacitance of Cload, with an output voltage swing Vswing (=V1-V0 for the logic levels 1 and 0) and a speed requirement about maximum rise/fall time Trf: in this case the requirement for the minimum current (to be compliant with Trf) is
Imin = NxCloadxVswing / Trf
so from the above relation considering the output current driving capability you are able to determine the maximum Fan Out (N) for this application, otherwise you will have to relaxe timings or to reduce the N.
The same considerations apply also to fan in, where Cload now is the input capacitance applied to the input port of the stage: but in this case you shall evaluate the input current driving capacity of the gate when a Vswing is applied.
Fan Out is the number of gates a gate is capable of driving.
What do you exactly mean "calculate". By the formulas given by some of the users, CMOS fanout would be close to infinity?
Fan Out is the number of gates a gate can drive.
So while Fan Out for TTL logic is around 10, which means if you connect more than 10 gates to an output of a TTL gate, chances are, they wont be driven by correct logic
Whereas in CMOS you can almost connect 1000s of gate. A single gate is capable of driveing thousands of gates but with each gate added, its propogation delay is going to increase, so here the limiting factor is propagation delay as opposed to the current which is the limiting factor in TTL logic.
Added after 13 minutes:
number of fan out of a gate = number of output pin of the gate
If u read logical effort concept then u will understand clearly about fan in and fanout bcoz he has explained with the help of problems. The book is available in www.gigapedia.org ( u need to register there) and it is also available in this forum only so try to search it and find out
Fan in is always fixed for a gate.i.e the no. of inputs
Fan out is the no..of outputs the gate can drive successfully..
Fan out is determined by the internal design of the gate.
Different logic families like TTL, CMOS, ECL,SCHOTTKY will give you different fanout for the same gate..
to help you in understanding how fan in fan out influences designs take in consideration an example. Consider a driver loaded by N gates (N is the desired fan out), each one with input Capacitance of Cload, with an output voltage swing Vswing (=V1-V0 for the logic levels 1 and 0) and a speed requirement about maximum rise/fall time Trf: in this case the requirement for the minimum current (to be compliant with Trf) is
Imin = NxCloadxVswing / Trf
so from the above relation considering the output current driving capability you are able to determine the maximum Fan Out (N) for this application, otherwise you will have to relaxe timings or to reduce the N.
The same considerations apply also to fan in, where Cload now is the input capacitance applied to the input port of the stage: but in this case you shall evaluate the input current driving capacity of the gate when a Vswing is applied.
Fan in is the number of wires connected to the particular input pin.. and fanout is the number of wires or pins driven by the particular output pin of the cell.
You can check your netlist for the particular cell and find it out , or there are commands in the pnr or sta tool to find it out and varies from tool to tool.
fanout is the number of gates that can be connected to a single output pin of an ic, so that it can drive those gates (with the required current ratings) ..condition is that those gates must be of the same logic family..
you can experiment it out by calculating the fan out experimentally and then connecting different gates of other logic families..the results will vary..
ex- if you connected some other gates to a nand gate output pin of "nand gate ic", you will get the fanout as specified in the ic's datasheet provided as by the current ratings as :
Iol(low level output current), Iil(low level input current), Ioh(high level output current), Iih(high level input current),,
keeping these in mind,, you can now understand fanout as this:
fanout(low)-the number of gates that a output pin can drive when the pin is at low state..
looking at the datasheet of 7400 ic..
i got Iol as 8mA and Iil as 0.4mA, Ioh as 400uA, Iih as 20uA...(you may confirm to the datasheet also for the values)
so fanout(low)=Iol/Iil
=20
fanout(high)-outputs from a single pin that can drive other gates while it is in high state..
=Ioh/Iih
=400/20=20
it is just a case that both are coming out to be the same,, otherwise if they are different,, lower value is used..
You can yourself verify these out...
for deeper studies:you may refer to some good books like of Digital Systems, Principles and application by Tocci and Moss... etc.....
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
